ÿØÿà JFIF    ÿÛ C    !"$"$ÿÛ C  ÿ p " ÿÄ     ÿÄ   ÿÚ   ÕÔË® (% aA*‚XYD¡(J„¡E¢RE,P€XYae )(E¤²€B¤R¥ BQ¤¢ X«)X…€¤  @ .............................................................................................................................................................................. ............................................................................. ÿØÿà JFIF    ÿÛ C    !"$"$ÿÛ C  ÿ p " ÿÄ     ÿÄ   ÿÚ   ÕÔË® (% aA*‚XYD¡(J„¡E¢RE,P€XYae )(E¤²€B¤R¥ BQ¤¢ X«)X…€¤  @ .............................................................................................................................................................................. ............................................................................. /* SPDX-License-Identifier: GPL-2.0 */ /* This file defines field values used by the versaclock 6 family * for defining output type */ #define VC5_LVPECL 0 #define VC5_CMOS 1 #define VC5_HCSL33 2 #define VC5_LVDS 3 #define VC5_CMOS2 4 #define VC5_CMOSD 5 #define VC5_HCSL25 6